Von Neumann architecture

Definition

The von Neumann architecture—also known as the von Neumann model or Princeton architecture—is a computer architecture based on the First Draft of a Report on the EDVAC, written by John von Neumann in 1945, describing designs discussed with John Mauchly and J. Presper Eckert at the University of Pennsylvania's Moore School of Electrical Engineering. The document describes a design architecture for an electronic digital computer made of "organs" that were later understood to have these components:A central arithmetic unit to perform arithmetic operations; A central control unit to sequence operations performed by the machine; Memory that stores data and instructions; An "outside recording medium" to store input to and output from the machine; Input and output mechanisms to transfer data between the memory and the outside recording medium.

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Dijkstra Electromechanics Electronic Delay Storage Automatic Calculator Electronic circuit Embedded system Endianness Entscheidungsproblem Executable Execution unit Explicit data graph execution Explicitly parallel instruction computing FIFO (electronic)FLOPS FORTRAN Fabric computing False sharing Field-programmable gate array Field-programmable object array Finite-state machine Finite-state machine with datapath First Draft of a Report on the EDVAC Floating-point unit Flowchart Flynn's taxonomy Functional programming Gate array General-purpose computing on graphics processing units Glue logic Gordon Bell Graphics processing unit Hardware acceleration Hardware register Hardware security module Hardwired control unit Harvard architecture Hazard (computer architecture)Herb Grosch Herman Goldstine Herman Lukoff Heterogeneous System Architecture Heterogeneous computing Hierarchical state machine High-Level Shader Language High-level programming language History of general-purpose CPUs Hyper-threading Hypercomputation IA-64 IAS machine IBM POWER architecture IBM SSEC IBM System/360 architecture IBM System/370 IBM System/390 ILLIAC Image processor Implementation Index register Input and output Institute for Advanced Study Instruction-level parallelism Instruction cache Instruction cycle Instruction decoder Instruction fetch Instruction pipelining Instruction set Instruction set architecture Instruction unit Instructions per cycle Instructions per second Integrated circuit Interconnect bottleneck J. Presper Eckert JOHNNIAC Jack Copeland Java virtual machine John Backus John Mauchly John von Neumann Jones & Bartlett Just-in-time compilation Kathleen Booth Kiev Institute of Electrotechnology Konrad Zuse Kyiv LISP Linker (computing)Little Man Computer Little man computer Loader (computing)Load–store architecture Load–store unit Locality of reference Logic gate Los Alamos National Laboratory Los Alamos Scientific Laboratory M32R MANIAC I MESM MIPS-X MIPS architecture MIT Press Main memory Manchester Baby Manchester Mark 1 Manhattan Project Manycore processor Martin Davis (mathematician)Mathematics Max Newman McGraw-Hill Book Company Memory-level parallelism Memory-mapped I/O Memory address register Memory buffer register Memory controller Memory dependence prediction Memory hierarchy Memory management unit Memory protection MicroBlaze Microarchitecture Microcode Microcontroller Microcontrollers Microprocessor Microprocessor chronology Minimal instruction set computer Mixed-signal integrated circuit Mobile processor Model of computation Modified Harvard architecture Moore School of Electrical Engineering Motorola 68000 series Multi-chip module Multi-core processor Multiple instruction, multiple data Multiple instruction, single data Multiplexer Multiprocessing Multiprocessor system on a chip Multithreading (computer architecture)National Physical Laboratory, UK Network on a chip Network processor Neuromorphic engineering No instruction set computing Non-uniform memory access Nondeterministic Turing machine ORACLE (computer)ORDVAC Oak Ridge National Laboratory Object-oriented programming One-instruction set computer OpenRISC Operand forwarding Orthogonal instruction set Out-of-order execution Oxford University Press PDP-11 architecture PERM (computer)Package on a package Parallel computing Patch cable Performance per watt Peripheral Physics processing unit Pilot ACE Pin grid array Pipeline stall Plugboard Pointer machine Post–Turing machine PowerPC Power ISA Power Management Unit Power management Power management integrated circuit Preemption (computing)Princeton, New Jersey Princeton University Press Probabilistic Turing machine Process (computing)Processor (computing)Processor design Processor register Program counter Programmable Array Logic Punched tape Quantum Turing machine Quantum cellular automaton Quantum circuit Quantum computing Quantum logic gate Queue automaton RAND Corporation RISC-V ROM image Random-access machine Random-access stored-program machine Re-order buffer Read-only memory Reduced instruction set computer Reduction to practice Register file Register machine Register renaming Register–memory architecture Rehovot Reservation station SEAC (computer)SILLIAC SPARC SUPS SWAC (computer)SWAR Scalar processor Scoreboarding Scratchpad memory Secondary storage Secure cryptoprocessor Selectron tube Self-modifying code Self-replicating machine Semiconductor device fabrication Sequential logic Simultaneous and heterogeneous multithreading Simultaneous multithreading Single-core Single instruction, multiple data Single instruction, multiple threads Single instruction, single data Single program, multiple data Soft microprocessor Speculative execution Speculative multithreading Stack machine Stack register Stan Frankel Stanford MIPS Status register Stored-program computer Stream processing Structural hazard Sum-addressed decoder SuperH Supercomputer Superscalar processor Switch System bus System in a package System on a chip TRIPS architecture Task parallelism Temporal multithreading Tensor Processing Unit Thread (computing)Three-dimensional integrated circuit Throughput Tick–tock model Tile processor Tomasulo's algorithm Transactions per second Transistor count Translation lookaside buffer Transport triggered architecture Turing Award Turing machine UNIVAC 1101 Ukrainian Soviet Socialist Republic Ultra-low-voltage processor Unicore Uniform memory access United States patent law Universal Turing machine University of Cambridge University of Illinois Urbana-Champaign University of London University of Manchester University of Pennsylvania VAX VISC architecture Vacuum tube Vector processor Very long instruction word Victoria University of Manchester Virtual memory Vision processing unit W. W. Norton & Company W. W. Norton & Company Inc.WEIZAC Wait state Web browsers Weizmann Institute of Science Whirlwind (computer)Wide-issue Williams tube Word (computer architecture)Word processor Write buffer X86 Z/Architecture Zeno machine Zero instruction set computer

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